1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a memory cell array and, more particularly, to the semiconductor integrated circuit that can detect and identify a shortcircuit between a storage node and a power terminal in a memory cell to thereby improve the production yield.
2. Description of Related Art
FIG. 16 is a circuit diagram of a conventional SRAM memory cell in a semiconductor integrated circuit (referred to below as an IC device). FIG. 17 shows a microshort between a positive supply terminal and a memory node B in the memory cell shown in FIG. 16, and FIG. 18 shows a microshort between a memory node A and a negative supply terminal.
As shown in FIG. 17, microshorts can occur between memory node B of the memory cell 100 and the positive supply terminal 101 of the cell to which positive supply voltage VCCM is applied during the memory cell manufacturing process of an IC device due to the inclusion of etching remnants and other foreign matter. A high resistance 108 is thus produced where the microshort occurs, and the positive supply terminal 101 and memory node B of the memory cell are thus connected by this high resistance 108.
A microshort can likewise occur during the memory cell manufacturing process of an IC device due to the inclusion of etching remnants and other foreign matter between the grounded negative supply terminal 102 of the memory cell and memory node A of the memory cell 100 as shown in FIG. 18. A high resistance 108 is likewise formed where the microshort occurs, and memory node A and the negative supply terminal 102 are thus connected by this high resistance 108.
When the voltage level of memory node B, which is the node between the drain of p-channel MOS transistor 104 (referred to as simply a PMOS transistor below) and the drain of n-channel MOS transistor 106 (referred to as simply an NMOS transistor below), goes low, current flows from positive supply terminal 101 of the memory cell through high resistance 108 and NMOS transistor 106 to ground. Because this through-current flows even when the memory cell is in the standby mode, the semiconductor chip in which the SRAM device is formed will have a standby state error.
When the resistance of this high resistance 108 is sufficiently high compared with the on resistance of NMOS transistor 106, there is no particular effect with respect to the function of the semiconductor chip itself, and it is apparent only as an increase in the standby current of the semiconductor chip. This means that the memory cell in which the standby current increases cannot be identified, even semiconductor chips having a redundancy circuit cannot be salvaged, and ultimately the chip must be treated as defective.
Furthermore, when node A, i.e., the node between the drain of PMOS 103 and the drain of NMOS 105, goes high, current flows from positive supply terminal 101 of the memory cell through PMOS 103 and high resistance 108 to ground as shown in FIG. 18. Because this through-current flows even when the memory cell is in the standby mode, the semiconductor chip in which the SRAM device is formed will have a standby state error.
When the resistance of this high resistance 108 is sufficiently high compared with the on resistance of PMOS transistor 103, there is no particular effect with respect to the function of the semiconductor chip itself, and it is apparent only as an increase in the standby current of the semiconductor chip. This means that the memory cell in which the standby current increases cannot be identified, even semiconductor chips having a redundancy circuit cannot be salvaged, and ultimately the chip must be treated as defective.
By providing power supply pads 111 and 112 for memory cell array 123, and power supply pads 113, 114 for peripheral circuits 121, 122, as shown in FIG. 19, however, it is possible to detect whether the standby current leak originates in peripheral circuits 121, 122 or memory cell array 123. This information can then be used for process improvement. However, if the standby current defect is due to a fault in the memory cell array 123, it is still difficult using the configuration shown in FIG. 19 to identify which memory cell in the memory cell array 123 is at fault, and it is therefore still not possible to salvage the chip using the redundant circuit.
Japanese Patent Laid-open Publication No. 8-45299 teaches a method for detecting dc current faults in a semiconductor memory device and memory cell, and Japanese Patent Laid-open Publication No. 8-138399 teaches a semiconductor device designed to recover from standby current errors. It is important to note, however, that both of these disclosures differ from the present invention in that they do not teach a method for identifying the defective memory cell as part of a chip salvage technique.
Considering the aforementioned problem, it is therefore an object of the present invention to provide a semiconductor integrated circuit whereby the defective memory cell can be identified when a standby current defect or other dc current leak occurs, and semiconductor chip production yield can therefore be improved.
To achieve this object, each memory cell of a semiconductor integrated circuit having a memory cell array of SRAM memory cells according to the present invention comprises a first positive supply terminal to which a specific first positive supply voltage is applied during wafer testing; a second positive supply terminal to which a specific second positive supply voltage is applied during wafer testing; a negative supply terminal to which a specific negative supply voltage is applied; a first inverter circuit of which the supply voltages applied to the first positive supply terminal and negative supply terminal are the power supply; and a second inverter circuit of which the supply voltages applied to the second positive supply terminal and negative supply terminal are the power supply.
Preferably in this case, a specific positive supply voltage is applied during normal operation to the first positive supply terminal and second positive supply terminal.
Yet further preferably, each memory cell also has an n-well voltage input terminal whereby an n-well voltage is applied to each MOS transistor of the first and second inverter circuits.
Yet further preferably, the first positive supply voltage or the second positive supply voltage, whichever higher, is applied to the n-well voltage input terminal during wafer testing.
In a further semiconductor integrated circuit having a memory cell array of SRAM memory cells according to the present invention, each memory cell comprises a positive supply terminal to which a specific positive supply voltage is applied; a first negative supply terminal to which a specific first negative supply voltage is applied during wafer testing; a second negative supply terminal to which a specific second negative supply voltage is applied during wafer testing; a first inverter circuit of which the supply voltages applied to the positive supply terminal and first negative supply terminal are a power supply; and a second inverter circuit of which the supply voltages applied to the positive supply terminal and second negative supply terminal are a power supply.
Preferably in this case a specific negative supply voltage is applied during normal operation to the first negative supply terminal and second negative supply terminal.
Yet further preferably, each memory cell further comprises a p-well voltage input terminal whereby a p-well voltage is applied to each MOS transistor of the first and second inverter circuits.
Yet further preferably, the first negative supply voltage or the second negative supply voltage, whichever lower, is applied to the p-well voltage input terminal during wafer testing.
In yet a further semiconductor integrated circuit having a memory cell array of SRAM memory cells according to the present invention, each memory cell comprises a first positive supply terminal to which a specific first positive supply voltage is applied during wafer testing; a first negative supply terminal to which a specific first negative supply voltage is applied during wafer testing; a second positive supply terminal to which a specific second positive supply voltage is applied during wafer testing; a second negative supply terminal to which a specific second negative supply voltage is applied during wafer testing; a first inverter circuit of which the supply voltages applied to the first positive supply terminal and first negative supply terminal are a power supply; and a second inverter circuit of which the supply voltages applied to the second positive supply terminal and second negative supply terminal are a power supply.
In this semiconductor integrated circuit, a specific positive supply voltage is preferably applied during normal operation to the first positive supply terminal and second positive supply terminal, and a specific negative supply voltage is applied during normal operation to the first negative supply terminal and second negative supply terminal.
Yet further preferably, each memory cell further comprises an n-well voltage input terminal whereby an n-well voltage is applied to each MOS transistor of the first and second inverter circuits, and a p-well voltage input terminal whereby a p-well voltage is applied to each MOS transistor of the first and second inverter circuits.
Yet further preferably, the first positive supply voltage or the second positive supply voltage, whichever higher, is applied to the n-well voltage input terminal, and the lesser of the first negative supply voltage and the second negative supply voltage is applied to the p-well voltage input terminal, during wafer testing.
Yet further preferably, the semiconductor integrated circuit further comprises a corresponding fuse for breaking each line disposed for applying the first positive supply voltage and second positive supply voltage to each specific memory cell group of the memory cell array.
Yet further preferably, the semiconductor integrated circuit further comprises a corresponding fuse for breaking each line disposed for applying the first negative supply voltage and second negative supply voltage to each specific memory cell group of the memory cell array.
Further preferably, the fuses are arranged alternately above and below or right and left to the memory cell array.
Yet further preferably, the lines are disposed in two layers, and the fuses are disposed to each line in each layer.
Yet further preferably, each memory cell of the memory cell array is a CMOS device.
Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings.